The present invention relates to a clamping circuit and, more particularly, to a clamping circuit coupled with a signal line and clamping and adjusting a level of a transmitted signal at a predetermined voltage.
A conventional clamping circuit for clamping a voltage level of a clamp output node connected to a signal line has a detecting stage for detecting a voltage at the clamp output node and a feedback stage having a first and second feedback path for charging or discharging the node, respectively, according to the detected voltage. The detecting stage is usually constructed by using a differential amplifier having one input node connected to the clamp output node and another connected to a reference voltage terminal. One output of the differential amplifier controls a gate circuit which constitutes the first feedback path for supplying a current from a power supply terminal to the clamp output node. Another output of the differential amplifier selectively activates the second feedback path having current mirror circuit. That is, the current mirror circuits is supplied with an input current thereof by the differential amplifier and, accordingly, pulls a current from the clamp output node and provides it to a ground terminal. The clamping circuit also has a current source section responsive to a clamp control signal for supplying a constant current to the differential amplifier. Therefore, the activation of the clamping circuit is controlled by the clamp control circuit.
An example of conventional clamping circuit coupled with a signal line is shown in FIG. 1. A clamping circuit having a clamping section 7 and a current source IS1 is connected to a signal line L1. In FIG. 1, other clamping circuits each having clamping section 8 or 9 are also coupled with signal lines L2 and L3 to provide a three channel signal transmitting circuit. As for the signal line L1, for example, it has an output terminal 5 which is directly connected to a clamp output node N1 of the clamping section 7 and connected to an input terminal 6 via a capacitor C1. To the input terminal 6, an analog signal to be transmitted is supplied. The signal is, for example, a composite video signal having horizontal scan periods and blanking periods appearing alternately. In this case, the signal lines L1, L2 and L3 correspond to three primary colors respectively.
In the clamping section 7, transistor Q3 having its base electrode to the clamp output node N1 and transistor Q4 having its base to a clamp voltage terminal 2 supplying a clamp voltage Vcl are coupled to each other to form a differential amplifier. The emitter electrodes of the transistor Q3 and Q4 are commonly connected to a transistor Q13 in a current source section IS1 which is controlled by a current control section IC1. The current control circuit IC1 is supplied with a clamp control signal Scl from a clamp control terminal 1 and activates the current source section IS1 when the clamp control signal Scl is at High level. That is, the clamping circuit shown in FIG. 1 is selectively activated to clamp a voltage of the node N1 by the clamp control signal Scl.
The collector electrode of the transistor Q4 is connected to a base electrode of a transistor Q5. When the voltage at the node N1 is lower than the clamp voltage Vcl, the collector voltage of the transistor Q4 falls and the pnp-type transistor Q5 increases a current from a power terminal Vcc to the clamp output node N1, thereby increasing the voltage of the node N1. The collector electrode of the transistor Q3 is connected to collector and base electrodes of a transistor Q2.
When the voltage at the node N1 is higher than the clamp voltage Vcl, the transistor Q3 increases base and collector currents of the transistor Q2. A transistor Q1 in combination with the transistor Q2 forms a current mirror circuit and also increases its output current from the power terminal 3 to a node N2. The increased current to the node N2 is supplied to a transistor Q8 and flows to the ground terminal 4. A transistor Q7 in combination with the transistor Q8 forms another current mirror circuit and increases its collector current from the clamp output node N1 to the ground terminal 4, decreasing the voltage of the node N1. Therefore the clamping circuit clamps and maintains the voltage of the node N1 at the predetermined clamp voltage Vcl. When the clamp control signal Scl is at Low level, the transistors Q5 and Q7 are supplied with no base currents and, therefore, are in nonconductive states. The transistor Q3 is also in nonconductive state and no base current flows through the transistor Q3. Therefore, the voltage of the node N1 is maintained at the clamp voltage Vcl.
When the voltage of the node N1 is equal to the clamp voltage Vcl, the transistors Q3 and Q4 are conductive and provide base currents of the transistors Q1, Q2, Q5 and Q6. The transistor Q1 provides base currents of the transistors Q7 and Q8. Therefore, in this case, each of the transistors Q1 to Q8 allow its collector current to flow stably. That is, the collector currents of the transistors Q3, Q4, Q7 and Q8 are provided to the ground terminal 4 stably.
In this case, the operation of the clamping circuit for clamping the voltage of the node N1 is performed during the blanking interval of the composite video signal supplied to the input terminal 6. That is, the clamp control signal Scl is synchronized with the composite video signal in such a manner that the control signal Scl takes its High level during the blanking interval of the video signal. During the blanking period, the video signal supplied to the input terminal 6 takes, for example, its maximum voltage level Vmax. At the same time, the clamping circuit clamps the voltage of the node N1 at the clamp voltage Vcl. Therefore the capacitor C1 is charged according to a voltage difference between the maximum voltage level Vmax and the clamp voltage Vcl. When the blanking period is over and the following horizontal scan periods starts, the node N1 in the clamping section 7 is rendered to be in a floating state. Therefore, the voltage level of the input video signal supplied to the input terminal 6 is shifted as a whole to have its maximum voltage exactly equal to the clamp voltage Vcl and transmitted to the output terminal 5.
However, in the conventional clamping circuit, the clamping section 7 necessitates current mirror circuits for constituting a feedback path to discharge the clamp output node N1 and causes increase in number of circuit elements or total circuit area. Moreover, owing to the current mirror circuits, the feedback operation takes a long time and decreases the operation speed of the clamping circuit. Furthermore, owing to the current mirror circuits, in particular to those having the transistors Q7 and Q8, which makes stable currents to the ground terminal, the current consumption of the clamping circuit becomes very large. The feed back operation taking a long time also causes a large current consumption at the current source section IS1 and the current mirror circuit having the transistors Q7 and Q8. In particular, in case where the clamping circuit is applied to a signal transmitting circuit and coupled with a signal line for transmitting a composite video signal, the conventional clamping circuit necessitates a long blanking period and decreases the total operation speed of the signal transmitting circuit.